1. Technical Field
The present application generally relates to ESD protections and, more specifically, to the use of nanotube switching elements in the formation of circuits for enhanced electrostatic discharge (EDS) protection of semiconductor, hybrid semiconductor and nanotube, and nanotube-only circuits.
2. Discussion of Related Art
Electrical overstress resulting from electrostatic discharge (ESD) is a major problem in every generation of electronic devices, resulting in oxide and junction failures such as series resistor rupture, open circuits and short circuits, for example. Nanotube resistors may be used to replace presently used series resistors such as polysilicon, for example, and improve protective device resistance to ESD-induced failure.
FIG. 1 illustrates a prior art protective device (PD) schematic 10 that includes a series resistor 16 and semiconductor diodes 18. An ESD pulse applied to the input pad 12 is attenuated by resistor 16 and semiconductor diodes 18, reducing the ESD voltage applied to node 17, thereby preventing damage to protected circuits 14 as described in the referenced book H. B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI,” Addison-Wesley Publishing Company, 1990, pages 46-51. For some input or output pads there is no series resistance 16, and only semiconductor diodes 18 are used. Resistor 16 may be fabricated using polysilicon or diffusion layers, for example, or other suitable resistive material, and may be in the range of 10 to 100,000 ohms, for example. Conventional resistors fabricated using polysilicon or diffusion layers, for example, can fail in the presence of an ESD pulse, with the resistor becoming an open circuit, for example, due to a combination of current density and temperature.
Prior art protective device structures 10 such as those illustrated schematically in FIG. 1 have high relative capacitance values, 1.5 pF, for example, as described in Bertin et. al. U.S. Pat. No. 6,141,245. If an output driver drives eight chips in parallel as in a memory address line, for example, then the protective device contribution to the capacitive loading is 12 pF. FIG. 3 illustrates prior art structure 39 illustrated in U.S. Pat. No. 6,141,245 in which a fuse 40 is added in series with prior art protective devices, along with a fuse pad, such that current can be forced between the input pad and the fuse pad. After the component is installed in a system, current is forced through the fuse until it open-circuits disconnecting the protective device from the protected circuits to reduce capacitance loading, as described in U.S. Pat. No. 6,141,245. The component cannot be removed and handled again without a high risk of ESD damage because the fuse blow operation is irreversible.
Carbon nanotubes can tolerate current densities in excess of 100 times the current densities of copper, exhibit high thermal conductivity, and do not fail due to overheating as described in the reference Srivastava and Banerjee, “A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies,” Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), September 39-October 2, Waikoloa, Hi., pp. 393-398, 2004. These, and other properties of carbon nanotubes are described in Nantero carbon nanotube patents, patent publications, dockets, etc. herein incorporated.